1. Field of the Invention
The present invention relates to a phase detector that detects a shift of a phase of a comparison clock with respect to a phase of a reference clock, a phase comparator that detects phase delay and phase advance, and a clock synchronizing device that synchronizes the phases of both the clocks.
2. Description of the Related Art
A clock generator represented by a phase locked loop (hereinafter referred to as “PLL”) and a delay locked loop (hereinafter referred to as “DLL”) in a clock synchronizing system is an element circuit indispensable for keeping synchronization between external data (an external clock) and an internal clock. It is extremely important in constructing a stable clock synchronizing system to accurately adjust a phase relation between the external clock and the internal clock with the clock generator.
FIG. 8 is a block diagram of a configuration of a DLL in a digital system shown as an example of the clock generator. This DLL includes a phase comparator 1 that compares a phase difference between an external clock CLKEXT and an internal clock CLKINT, an up/down counter (hereinafter referred to as “counter”) 2 that controls delay time according to output signals UP and DN from the phase comparator 1, and a delay line 3 and a clock driver 4 that perform adjustment of the delay time.
FIG. 9 is a circuit diagram of an example of a delay unit that configures a delay line. The delay unit includes inverters INV1, INV2, and INV3, switches SW1 and SW2, and capacitors C1 and C2. In this delay line, connection and disconnection of the capacitors C1 and C2 to and from the delay line are switched according to a level of an output signal n bit from the counter 2 shown in FIG. 8, whereby adjustment of a delay amount is realized.
FIG. 10 is a timing chart of the digital DLL. An operation principle of phase adjustment is explained with reference to this timing chart. When the internal clock CLKINT is delayed from the external clock CLKEXT (a period 1 shown in FIG. 10), the signal DN is at an “H” level, the counter 2 shown in FIG. 8 counts down, the capacitors for delay adjustment (the capacitors C1 and C2 shown in FIG. 9) are disconnected from the delay line one after the other, and the phase difference between the external clock CLKEXT and the internal clock CLKINT is narrowed.
Conversely, when the internal clock CLKINT overtakes the external clock CLKEXT (a period 2 shown in FIG. 10), the signal UP is at the “H” level, the counter 2 shown in FIG. 8 counts up, the capacitors for delay adjustment (the capacitors C1 and C2 shown in FIG. 9) are connected to the delay line one after the other, and the phase difference between the external clock CLKEXT and the internal clock CLKINT is narrowed.
With the configuration and the operations explained above, the phase difference between the external clock CLKEXT and the internal clock CLKINT is apparently brought closer to zero. Accuracy of bringing the phase difference closer to zero substantially depends upon the accuracy of the phase comparator 1. In other words, to design a highly accurate clock generator, it is necessary to design the phase comparator 1 that can highly accurately detect the phase difference between the external clock CLKEXT and the internal clock CLKINT.
FIG. 11 is a diagram for explaining a phase comparator in the past. FIG. 12 is a diagram for explaining input and output waveforms of the phase comparator in the past. As shown in FIG. 11, in the phase comparator in the past, a D type flip-flop (hereinafter referred to as “DFF”) is used. The internal clock CLKINT is connected as a data signal D and the external clock CLKEXT is connected as a clock signal CK. The signal UP is connected to a positive phase output Q and the signal DN is connected to a negative phase output Qb.
As shown in FIG. 12, when the internal clock CLKINT is delayed from the external clock CLKEXT, the signal DN is at the “H” level. When the internal clock CLKINT is advanced from the external clock CLKEXT, the signal UP is at the “H” level. Therefore, it is seen that a function of the phase comparator is realized. In this configuration, narrowing of a dead zone of the DFF directly leads to an increase in accuracy of phase difference detection. Therefore, it is possible to improve accuracy of phase detection by using a dynamic DFF that responds at high speed and has a narrow dead zone.
FIG. 13 is a circuit diagram of an example of the dynamic DFF. This circuit is a true signal phase clock (hereinafter referred to as “TSPC”) DFF. The dynamic DFF is actuated only with a positive phase clock to realize high speed and a narrow dead zone.
The DFF includes a first latch circuit L1 including a first p-channel transistor P1, a second p-channel transistor P2, and a first n-channel transistor N1, a second latch circuit L2 including a third p-channel transistor P3, a second n-channel transistor N2, and a third n-channel transistor N3, a third latch circuit L3 including a fourth p-channel transistor P4, a fourth n-channel transistor N4, and a fifth n-channel transistor N5, and an inverter INV 4.
A data signal D is connected to gates of the first p-channel transistor P1 and the first n-channel transistor N1. A clock signal CK is connected to gates of the second p-channel transistor P2, the third p-channel transistor P3, the third n-channel transistor N3, and the fourth n-channel transistor N4.
An output signal NC of the first latch circuit L1 is connected to a gate of the second n-channel transistor N2. An output signal X of the second latch circuit L2 is connected to gates of the fourth p-channel transistor P4 and the fifth n-channel transistor N5.
FIG. 14 is a timing chart in capturing an “L” level of the data signal D of the DFF. When the data signal D and the clock signal CK changes to the “L” level, an internal node NC changes to the “H” level. In response to this, the second n-channel transistor N2 is turned on and an internal node A also changes to the “H” level.
When the clock signal CK changes to the “H” level, the internal node NC changes to a floating state. Since the third n-channel transistor N3 is turned on at this timing, the internal node A changes to the “L” level. The level of the internal node NC in the floating state falls being affected by coupling due to a gate capacity of the second n-channel transistor N2. Therefore, mutual conductance gm of the second n-channel transistor N2 falls, a signal change in an internal node X slows down, and a delay occurs between rising timing of the clock signal CK and an “L” output.
A difference between time until the internal node NC changes to the “L” level in response to the rise of the data signal D and the second n-channel transistor N2 is turned off and time from the rise of the clock signal CK until the internal node X changes to the “L” level is considered to be a margin of data hold time. Therefore, the margin of the data hold time is spoiled by the fall of the internal node NC to an intermediate level in response to the rise of the clock signal CK. In other words, the performance of the high speed and the narrow dead zone is spoiled by the presence of a floating node in the inside.
As an example of improvement of the TSPC-DFF, in the past, there is disclosed a technique for connecting an n-channel transistor for pull-down to the internal node NC and controlling a gate level thereof with a signal obtained by delaying the clock signal CK (see, JP-A-2005-318479).
As shown in FIG. 11, when the phase comparator is simply realized by one DFF, if dead zone width of the DFF decreases to be shorter than delay time controllable by the delay unit shown in FIG. 9, the DFF repeats count-up and count-down and a phase is not locked. Therefore, it is difficult to narrow the dead zone width of the DFF itself more than necessary. From such a viewpoint, a phase comparator shown in FIG. 15 is also used. In this phase comparator, a period in which UP (or DOWN) is “H” corresponds to a phase difference. When both UP and DOWN rise, a flip-flop is reset and both UP and DOWN fall (see FIG. 16).